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MM74C90 * MM74C93 4-Bit Decade Counter * 4-Bit Binary Counter
October 1987 Revised May 2002
MM74C90 * MM74C93 4-Bit Decade Counter * 4-Bit Binary Counter
General Description
The MM74C90 decade counter and the MM74C93 binary counter and complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. The 4-bit decade counter can reset to zero or preset to nine by applying appropriate logic level on the R01, R02, R91 and R92 inputs. Also, a separate flip-flop on the A-bit enables the user to operate it as a divide-by-2, 5 or 10 frequency counter. The 4-bit binary counter can be reset to zero by applying high logic level on inputs R01 and R02, and a separate flip-flop on the A-bit enables the user to operate it as a divide-by-2, -8, or -16 divider. Counting occurs on the negative going edge of the input pulse. All inputs are protected against static discharge damage.
Features
s Wide supply voltage range: 3V to 15V s Guaranteed noise margin: 1V s High noise immunity: 0.45 VCC (typ.) s Low power compatibility: Fan out of 2 TTL driving 74L s The MM74C93 follows the MM74L93 Pinout
Ordering Code:
Order Number MM74C90N MM74C93N Package Number N14A N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Connection Diagrams
MM74C90 MM74C93
Top View
Top View
(c) 2002 Fairchild Semiconductor Corporation
DS005889
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MM74C90 * MM74C93
Logic Diagrams
MM74C90 MM74C93
Truth Tables
MM74C90 4-Bit Decade Counter BCD Count Sequence Count QD 0 1 2 3 4 5 6 7 8 9 L L L L L L L L H H Output QC L L L L H H H H L L QB L L H H L L H H L L QA L H L H L H L H L H 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MM74C93 4-Bit Binary Counter Binary Count Sequence Count QD L L L L L L L L H H H H H H H H Output QC L L L L H H H H L L L L H H H H QB L L H H L L H H L L H H L L H H QA L H L H L H L H L H L H L H L H
Output QA is connected to Input B for BCD count. H = HIGH Level L = LOW Level X = Irrelevant
Output QA is connected to input B for binary count sequence. H = HIGH Level L = LOW Level X = Irrelevant
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MM74C90 * MM74C93
Function Tables
Reset/Count Function Table Reset Inputs R01 H H X X L L X R02 H H X L X X L R91 L X H X L X L R92 X L H L X L X QD L L H Output QC L L L Count Count Count Count QB L L L QA L L H
Reset/Count Function Table Reset Inputs R01 H L X R02 H X L QD L QC L Count Count QB L QA L Output
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MM74C90 * MM74C93
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin (Note 1) Operating Temperature Range (TA) MM74C90, MM74C93 Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range Absolute Maximum VCC Storage Temperature Range (TS) Lead Temperature (TL) (Soldering, 10 seconds) 260C 700 mW 500 mW 3V to 15V 18V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range", they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
-0.3V to VCC +0.3V -55C to +125C
-65C to +150C
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Logical "1" Input Current Logical "0" Input Current Supply Current Logical "1" Input Voltage MM74C90, MM74C93 Logical "0" Input Voltage MM74C90, MM74C93 Logical "1" Output Voltage MM74C90, MM74C93 Logical "0" Output Voltage MM74C90, MM74C93 ISOURCE ISOURCE ISINK ISINK Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) VCC = 4.75V, IO = -360 A VCC = 5V, VOUT = 0V TA = 25C VCC = 10V, VOUT = 0V TA = 25C VCC = 5V, VOUT = VCC TA = 25C VCC = 10V, VOUT = VCC TA = 25C 0.4 V VCC = 4.75V, IO = -360 A 2.4 V VCC = 4.75V 0.8 V VCC = 4.75V VCC-1.5 V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V, IO = -10 A VCC = 10V, IO = -10 A VCC = 5V, IO = +10 A VCC = 10V, IO = +10 A VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V -1.0 0.005 -0.005 0.05 300 4.5 9.0 0.5 1.0 1.0 3.5 8.0 1.5 2.0 V V V V A A A Min Typ Max Units
CMOS/LPTTL INTERFACE
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) -1.75 -8.0 1.75 8.0 -3.3 -15 3.6 16 mA mA mA mA
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MM74C90 * MM74C93
AC Electrical Characteristics
TA = 25C, CL = 50 pF, unless otherwise specified Symbol tpd0, tpd1 tpd0, tpd1 tpd0, tpd1 tpd0, tpd1 tpd0, tpd1 tpd0, tpd1 tpd0, tpd1 tpd0, tpd1 Parameter Propagation Delay Time from AIN to QA Propagation Delay Time from AIN to QB (MM74C93) Propagation Delay Time from AIN to QB (MM74C90) Propagation Delay Time from AIN to QC (MM74C93) Propagation Delay Time from AIN to QC (MM74C93) Propagation Delay Time from AIN to QD (MM74C93) Propagation Delay Time from AIN to QD (MM74C90) Propagation Delay Time from R01 or R02 to QA, QB, QC or QD (MM74C93) tpd0, tpd1 Propagation Delay Time from R01 or R02 to QA, QB, QC or QD (MM74C90) tpd0, tpd1 Propagation Delay Time from R91 or R92 to QA or QD (MM74C90) tPW tPW tPW tr , tf tW fMAX CIN CPD Min. R01 or R02 Pulse Width (MM74C93) Min. R01 or R02 Pulse Width (MM74C90) Min. R91 or R92 Pulse Width (MM74C90) Maximum Clock Rise and Fall Time Minimum Clock Pulse Width Maximum Clock Frequency Input Capacitance Power Dissipation Capacitance
(Note 2)
Conditions Min Typ 200 80 450 160 450 160 500 200 500 200 600 250 450 160 150 75 200 75 250 100 600 30 600 300 500 250 250 125 250 125 200 100 15 5 250 100 2 5 5 45 100 50 Max 400 150 850 300 800 300 1050 400 1000 400 1200 500 800 300 300 150 400 150 500 200 Units ns ns ns ns ns ns ns ns
VCC = 5V VCC = 10 VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10 VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 10V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V Any Input (Note 3) Per Package (Note 4)
ns
ns
ns ns ns s ns MHz pF pF
Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load ac power consumption of any CMOS device. For complete explanation see Family Characteristics application note-- AN-90.
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MM74C90 * MM74C93
AC Test Circuits
MM74C90 MM74C93
Clock rise and fall time tr = tf = 20 ns
Clock rise and fall time tr = tf = 20 ns
Switching Time Waveforms
MM74C90 and MM74C93 are solid line waveforms. Dashed line waveforms are for MM74C90 only.
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MM74C90 * MM74C93 4-Bit Decade Counter * 4-Bit Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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